Presently, there are various approaches to treating conductive layers for eventual utilization in printed circuit boards and cards (hereinafter also simply referred to as PCBs), chip carriers and the like substrates. Examples of same are described below, including within the several patents listed. With respect to the circuit (wiring) patterns being formed on many types of substrates, particularly PCBs (including those known as “high speed” boards described below), line widths may now be as small as ten-odd microns. Accordingly, the conductive layers (some also referred to as metal “foils” in the art) are becoming much thinner than those which produced wider lines in previous substrates. By way of example, when the designated thickness of metal foil for use in the formation of the conventional wiring pattern of about 100 micron line width has ranged from about 15 to 35 microns, the thickness of metal foil utilized in the formation of ten-odd micron wiring patterns must be reduced correspondingly. To accomplish this, an aluminum or copper foil may be used. Preferably, copper is used, especially an electrodeposited copper foil, produced by electrodepositing copper on a drum surface.
With respect to such electrodeposited copper foil, the surface at which copper deposition is initiated (the surface in contact with the drum) is referred to as the “shiny side”, and the surface at which copper deposition is completed is referred to as the “matte side”. The surface condition of the shiny side is substantially the same as that of the drum. That is, the RMS surface roughness value (a conventional measurement of metal surface roughness for layers used in PCBs; see more below) of the drum is from about 0.1 to 0.5 microns with a maximum peak to valley roughness value from about 1.0 to 2.0 microns. (Maximum peak to valley roughness is another means of characterizing surface roughness of a metal layer such as copper foil used in PCBs) As a result, the “shiny” side of the electrodeposited copper formed on this drum (and against the drum's outer surface) has a similar roughness. On the other hand, with respect to the outer matte side of the formed copper layer, its surface roughness is greater than the surface roughness of the shiny side, typically having an RMS value of from about 1.0 to about 2.0 microns with a maximum peak to valley roughness in the range of about 3.0 to 10 microns.
There are various different methods of characterizing surface roughness in the industry including Ra (average roughness or the arithmetic average above and below the center line in a segment), Rq (or RMS, which is the square root of the average of the squared absolute distances of the surface profile from the mean line), Rt (maximum peak to valley or the height difference between the highest and lowest points in a segment) and Rz (the 10 point average surface roughness). Unless otherwise specified, RMS (Rq) values will be used herein and simply referred to as “RMS roughness” for ease of explanation purposes.
With regard to conventional electrodeposited and similar copper foils, it is known to subject these foils to various treatments prior to inclusion thereof as part of a dielectric-conductive layer multilayered composite structure (these sometimes also referred to as “sub-composites” if used in combination with other “sub-composites” to form such a larger, multilayered product), including treating the foil for the purpose of increasing adhesion between the foil and dielectric layer(s) in the final structure. For example, mechanical polishing is a method of smoothing the surface of the copper foil with the use of mechanical means, usually in the form of a buffer. Unfortunately, if the foil is too thin, it may be damaged, e.g., severed or torn in sections, from the relatively high stresses exerted on the copper foil during this processing. Thus, mechanical polishing is only considered suitable for preparing the surface of relatively thick copper foils. In comparison, chemical and electrolytic polishing processes exert virtually no relatively high stresses on copper foils so it is believed that relatively thin foils may be successfully treated using one or both of these processes. However, such processes are typically expensive to operate, often requiring relatively expensive equipment, costly chemical baths, as well as prolonged periods during which the foil is so treated, thereby extending the total time of manufacture of the end product. It is also known to “treat” the surfaces of copper conductive foils (or sheets) by electroplating additional copper onto the surface to increase its roughness. Such plating may further involve electroplating minor amounts of chromium followed by a thin layer of zinc, this also increasing the roughness.
The use of properly faced conductive layers is especially important with respect to the aforementioned “high speed” substrate products. With operational requirements increasing for complex electronic components such as semiconductor chips which mount on circuitized substrates of the types cited above, so too must the host substrate be capable of handling these increased requirements. One particular increased requirement has been the need for higher frequency (high speed) connections between two or more such mounted components, which connections, as stated, occur through the underlying host substrate. By the term “high speed” as used herein is understood to mean signals within a frequency range of from about 3.0 to about 10.0 gigabits per second (GPS) and even higher.
Such high-speed connections are subjected to various detrimental effects, e.g., signal deterioration (also referred to as signal attenuation), caused by the inherent characteristics of such known substrate circuitry wiring. In the particular case of signal deterioration, this effect is expressed in terms of either the “rise time” or the “fall time” of the signal's response to a step change. The deterioration of the signal can be quantified with the formula (Z0 *C)/2, where Z0 is the transmission line characteristic impedance, and C is the amount of the connecting “via” capacitance (the “via” being a known plated hole within the substrate to couple different conductive layers). In a signal line (also referred to in the industry as a wire or trace) having a typical 50 ohm transmission line impedance, a plated thru-hole “via” having a capacitance of 4 pico-farads (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation. This compares to a 12.5 ps degradation with a 0.5 pf buried “via” of the various embodiments taught in the patent application cited above. This difference is significant in systems which operate at 800 MHz or faster (becoming the “norm” in today's technical world), where there are associated signal transition rates of 200 ps or faster.
One factor which can contribute to signal attenuation is, indeed, the surface roughness of the conductive layer through which the signals pass. As understood from the foregoing, PCB and other substrate manufacturers who laminate several dielectric and conductive layers to form the final board structure desire some level of roughness to promote adhesion between the two materials. Unfortunately, such roughness may also adversely affect signal passage if too excessive. As understood from the teachings herein, the instant invention is able to provide conductive layers with optimal roughness for sound adhesion to corresponding dielectric layers during bonding of such layers but also layers that are smooth enough that the surface irregularities of such layers do not significantly impede signal passage.
The teachings of the present invention are not limited to the manufacture of high speed substrates such as PCBs and the like, but are also applicable to the manufacture of substrates used for other purposes than high speed signal connections. Generally speaking, the teachings herein are applicable to any such substrates in which one or more conductive layers such as copper are bonded (e.g., laminated) to an adjacent dielectric layer and the resulting composite then used as the substrate, typically when combined with other dielectric and conductive layers to form a much thicker, built-up structure. The invention is able to provide a final structure in which signal attenuation is reduced while still assuring effective conductive layer and dielectric layer adhesion.
Examples of various methods for treating conductive layers and the products utilizing same are described in the U.S. Letters Patents and Japanese Patent Unexamined Publication listed below.
In U.S. Pat. No. 6,828,514 (Chan et al), assigned to the same Assignee as the present invention, there is defined a multilayered circuitized substrate including two multilayered portions, one of these able to electrically connect electronic components mounted on the substrate to assure high frequency connections there-between. The substrate may further include a “conventional” substrate portion of known materials so as to reduce costs while assuring a structure having an overall thickness deemed satisfactory for use in the respective product field.
In U.S. Pat. No. 6,475,638 (Mitsuhashi et al), there is described a process for producing an electrodeposited copper foil with its surface prepared which includes the steps of subjecting the foil having a shiny side and a matte side to at least one mechanical polishing so that the average surface roughness (Rz) of the matte side becomes in the range of 1.5 to 3.0 microns. The matte side is then subjected to a selective chemical polishing so that the average surface roughness (Rz) of the matte side becomes in the range of 0.8 to 2.5 microns. The mechanical polishing followed by chemical polishing of the matte side enables the foil to exhibit excellent properties, according to the authors.
In U.S. Pat. No. 6,291,081 (Kurabe et al), there is described a process for producing an electrodeposited copper foil including the steps of subjecting an electrodeposited copper foil having a shiny side and a matte side to a first mechanical polishing and then subjecting the matte side having undergone the first mechanical polishing to a further mechanical polishing. A planar, highly polished face with excellent surface properties is allegedly obtained. Moreover, depressed parts are not polished, so that the amount of copper lost by the polishing steps is extremely minute.
In U.S. Pat. No. 5,897,761 (Tagusari et al), there is described an electrodeposited copper foil for use in the manufacture of PCBs in which the original profile of the matte surface has been completely removed, preferably by buffing, leaving a surface having linear streaks and a certain roughness. The new surface is then given a nodule forming treatment which produces a second surface roughness, which may be followed by a corrosion resisting treatment. U.S. Pat. No. 5,858,517 (also Tagusari et al) also describes a similar process with what are considered minor modifications.
In U.S. Pat. No. 5,622,782 (Kovacs et al) there is described a foil having an adhesion promoting layer overlying at least one side of said foil. The adhesion promoting layer is suitable for enhancing adhesion between the foil and another substrate. The adhesion promoting layer is derived from a composition comprising silanes (A) and (B). Silane (A) is at least one compound including independently halogen, hydrocarbyloxy, or hydroxy groups and a hydrocarbon group or nitrogen-containing hydrocarbon group. Silane (B) is at least one compound including an organofunctional group being reactive with or having an affinity for said another substrate, and independently halogen, hydrocarbyloxy, or hydroxy groups.
In U.S. Pat. No. 5,545,466 (Saida et al), there is described a copper-clad laminate characterized in that an electrolytic copper foil on the glossy (shiny) surface side of which a copper electrodeposit is formed, is bonded at its glossy surface side to one side or each of both sides of a substrate, which has a fine-pitch wiring (circuit) pattern and exhibits a high etching factor. This patent is a continuation-in-part of U.S. Pat. No. 5,437,914 (Saida et al), below.
In U.S. Pat. No. 5,482,784 (Ohara et al), there is described a printed circuit inner-layer copper foil having inverted tear drop-shaped fine nodules formed on both surfaces of the copper foil, the nodules each having a specific length and maximum diameter.
In U.S. Pat. No. 5,437,914 (Saida et al), there is described a copper-clad laminate characterized in that an electrolytic copper foil on the glossy surface side of which a copper electrodeposit is formed is bonded at its glossy surface side to one side or each of both sides of a substrate.
In U.S. Pat. No. 5,096,522 (Kawachi et al), there is described a process for producing a copper-clad laminate which includes the steps of contacting the surface of a conductive carrier with a catalyst liquid containing a noble metal selected from the group consisting of Pd, Pt, Ru, Au, and Ag, subsequently forming a copper foil layer on the treated surface by copper electroplating, laminating an insulating base on the copper foil layer by hot-press bonding, and then separating the conductive carrier from the resulting laminate. The copper foil layer in the resulting copper-clad laminate is claimed to have fewer pinholes and allegedly exhibits isotropic mechanical characteristics.
In Japanese Patent Unexamined Publication Hei 5-160208, there is disclosed a tape carrier having a lead pattern formed from an electrodeposited copper foil wherein the overall surface of the foil's matte side has been polished. This publication describes the use of an electrodeposited copper foil whose 1-2 micron matte side surface profile has been chemically polished. It is mentioned that a highly reliable carrier tape with desired lead strength can be provided by the use of the copper foil whose matte side overall surface has been so chemically polished.
According to the teachings of the present invention, there is defined a method of treating conductive layers for use in circuitized substrate in which the conductive layers (e.g., electroplated copper foil) are adapted for mating with other layers and bonded (e.g., laminated) thereto. Surfaces of the conductive layers are roughened using this new process to the extent these surfaces fully bond to the dielectric to prevent subsequent delamination but not to the extent the surfaces adversely affect signal passage. These resulting conductive layers may function as ground, voltage and/or signal planes, depending on the operational requirements of the finished substrate. If a signal plane, the signal lines may be extremely thin and also extremely narrow in width, in which case these are still able to enable the passage of high speed signals there-through. As stated, however, the invention is not limited to substrates with extremely thin and narrow signal lines, as it is clear from the teachings herein that substrates having thicker and wider lines than defined herein may be successfully produced.
It is believed that such a method of treating such conductive layers and an associated method of making the substrate having one or more such layers therein will constitute significant advancements in the art.